eDiViDe (European Digital Virtual Design Lab)

In European companies and research institutes VHDL is the most popular language for the design of digital electronic systems. VHDL stands for VHSIC Hardware Description Language, in which VHSIC is the abbreviation of Very High Speed Integrated Circuit. In each partnering institute in this project (and also in many other European institutes of higher education) VHDL is part of the academic bachelor and master in electronics. The language can be used for the development of applications on both programmable and non-programmable chips. The most widely used programmable chips are FPGAs or Field Programmable Gate Arrays.

Decades of experience shows that the design of digital electronic applications needs a lot of practice. The classical way this is done, is by simulating digital designs, intended for implementation on programmable or non-programmable chips, using specific software on a PC. The verification of the developed design is done by checking the simulation results in a text format or as a digital waveform. This way of simulating a digital design is mostly experienced by students as being boring. Furthermore, a simulation-only verification approach causes the students to lose contact with reality, while the development of a real-life application is a big advantage for a future engineer.

To solve the limitations of simulation software, a real-life laboratory application can be driven by a programmable chip. The disadvantage of this way of learning is the overhead in time and money for the developers (i.e. usually the professors or assistants). Besides, the laboratory setup is only accessible within the institute and one setup does not offer sufficient variation in student exercises, assignments and projects.
In this project, we will develop a virtual laboratory that allows students to access several real-life setups whenever they are connected to the internet. These setups will be developed by the partnering institutes and will be made programmable through the internet using VHDL. Each setup will be accompanied by a camera that films the behaviour of the setup and sends back the result to the student. This way, the verification of the design is done by checking the behaviour of the application instead of digital simulation results.

The impact of the project is two-fold. On the one hand, the project prepares students for digital design in a company environment, which is very relevant, given the rapid digitalization of our society. It gives the partnering institutes the opportunity to deliver engineers with better skills in digital design. On the other hand, this project contributes to the visibility of the research activities in the partnering institutes, since each institute will focus on its own expertise in the development of the two advanced laboratory setups. Besides, the distributed laboratory will be made extensible such that other institutes can add their own laboratory setup. This way, the impact will grow beyond the project period.